1. Field of Invention
This invention relates to read/write channel circuits for magnetic disk drive systems, and more particularly to write precompensation circuits utilized when writing data to the magnetic disk drive.
2. Description of Related Art
In magnetic disk storage systems for computers, such as hard disk drives, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written in bit cells of a magnetic medium in concentric tracks. To write data to the disk, digital data is presented to a read/write amplifier which in turn provides positive or negative current to a head coil. Digital "1"s in the data stream cause transitions in the write current from one polarity to the other. Thus, data is written to the disk as abrupt transitions in the write signal polarity. To read this recorded data, the read/write head passes over the magnetic medium and transduces the recorded magnetic transitions into pulses and an analog signal that alternates in polarity. These pulses are then decoded by read/write channel circuitry to reproduce the digital data.
When writing the abrupt transitions to the disk, non-linear effects in the writing process may occur. For example, if two consecutive polarity transitions (a "11" pattern) are to be written to the disk, significant non-linear bit shift in the second transition and non-linear amplitude degradation in both transitions may occur. One method for compensating for the non-linear bit shift effects is to shift the location of the transition away from the nominal bit cell boundaries. This compensation technique is called write precompensation (WPC). The WPC circuitry delays the writing of certain "1"s to counter the non-linear bit shift effects. For example, when a "11" pattern is to be written, the WPC circuitry delays the writing of the second "1". In some cases it may be necessary to shift the transitions a significant fraction of the bit cell; therefore, a circuit which allows for a wide WPC range is desirable.
One prior art circuit for accomplishing write precompensation is shown in FIG. 1. As shown in FIG. 1, a write precompensation circuit 1 receives data to be written on a disk on a data input (line 10) and outputs data on the data output (line 30). The data is timed through a D Flip-Flop 20 which latches the data according to a timing signal 40. When desired, the timing signal 40 provides an appropriate timing delay to accomplish the necessary write precompensation. The timing signal 40 is generated by use of a zero delay clock 50 (C0 clock signal) and a delayed clock 60 (C1 clock signal). The C0 and C1 clock signals are provided to a clock multiplexer 70 which selects one of the clocks for timing the data signal in response to the select signal 80.
The clock signals C0 and C1 may be narrow pulse signals to allow the entire pulse to pass through the clock multiplexer 70 and to allow some delay in C0 vs. C1 without violating the setup and hold times of the multiplexer. A sample timing diagram for the write precompensation circuit 1 is shown in FIG. 1A. As shown in FIG. 1A, the pulse width of the clock signals is PW and the write precompensation (the delay between C0 and C1) is WPC. For an ideal multiplexer with zero setup and hold times, the maximum amount of WPC is: WPC.sub.max =T-PW. At high frequencies, PW is limited by the rise and fall times of the clocks since the entire pulse passes through the multiplexer before the state of the multiplexer may change. Because the rise and fall times may consume a significant percentage of select signal time T, the maximum amount of WPC may be undesirably limited. Thus, it would be desirable to utilize a write precompensation circuit that provides an improved WPC range.